1. Field of the Invention
The present invention relates generally to digital computer systems, and more specifically to a content addressable memory suitable for use with real time controllers and similar subsystems.
2. Description of the Prior Art
In digital real time control systems, a central processing unit is typically heavily burdened keeping track of timing, occurrence of events, and control of output signals. Examples of systems making use of real time controllers are automobile engine controllers, printers, computer disk and tape drive controllers, and electric motor controllers generally.
System designers generally attempt to have various parts of this system handle as much of the load as possible. This tends to minimize the burden on the central processor to keep up with the timing of numerous events. Various smart peripherals, timers, controllers, and so forth can be used to minimize the burden on the central processing unit. These peripheral subsystems typically perform functions related to handling simple, expected events.
It is common to have control events occur relative to a timer. This timer can be a real time timer, such as a time of day clock, or a counter incremented by regularly occurring external events such as rotation of a shaft. To keep track of scheduled control events, a content addressable memory can be used. A content addressable memory is a memory which is addressed by the value of the contents stored therein rather than by an address in an address space.
The various entries in the content addressable memory define times at which control events are to occur. The current value of a timer is compared to the contents of the content addressable memory, and a match between the current value of the timer and the contents of an entry in the memory indicate that a scheduled control event should occur at the present time.
Each entry in the content addressable memory typically has two fields. A comparison field contains the values to be compared to the timer or other inputs. An action field contains output values which are output when the input value matches with the comparison field.
In typical current systems, a standard random access memory plus lo decode logic is used as a substitute for a true content addressable memory. Each time a memory cycle occurs, each location in the random access memory is read. Typically, a counter is used to increment addresses into the random access memory, so that each location is read once for each memory cycle. The contents of a timer or other input are compared to the comparison field for each entry in the random access memory; if any matches occur the corresponding action field entry defines any actions to be taken. Such a subsystem is not a true content addressable memory, but behaves much as one for many purposes.
In a true content addressable memory, no memory addresses are generated. Each time a memory cycle occurs, an input value is compared simultaneously to the comparison field of every entry in the memory. No output is generated unless one or more entries in the content addressable memory have a comparison field value equivalent to the input value.
In order to read the contents of a memory location in the content addressable memory, an input value is applied to the memory. If there is a match with the contents of the comparison field of a memory entry, the rest of that memory entry can be read out. Specific entries in the memory are not easily accessed directly. Updating a content addressable memory tends to be very inefficient, and this is especially true when a random access memory is used as described above to model a content addressable memory. Updating or deleting specific entries in the content addressable memory can be difficult.
It would therefore be desirable to provide a true content addressable memory suitable for use with real time controllers and similar systems. It would be further desirable for selected entries in the memory to be easily accessed directly, in order to simplify memory updates and entry deletions.